A NEW HIGH SPEED, LOW POWER MODIFIED CURRENT CONTROLLED DOMINO LOGIC

Abstract

The demands of upcoming computing, as well as the challenges of nanometre of VLSI design
necessitate new digital logic techniques and styles that are at the same time high performance, energy
efficient and robust to noise and variation. Dynamic CMOS logic gates are broadly used to design high
performance circuits due to their high speed. Conversely, the vital demerit of dynamic logic style is its high
noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the pull down
network. With continuous technology scaling, this problem is getting more and more severe. This project is
proposed a new circuit for high speed and low power domino logic circuit. The conventional footed standard
domino logic is modified to add a new circuit to improve leakage tolerance, especially in the initial phase of
evaluation and discharge. Domino CMOS logic circuit family finds a wide variety of applications in
microprocessors, digital signal processors, and dynamic memory due to their high speed and low device
count. This project describes the new low power, noise tolerant and high speed domino logic technique and
presents a comparison result of this logic with previously reported schemes. The conditions for the
simulations are: CMOS 180 nm technology, 1V power supply and bottleneck operating temperature of 27ºC.

Author

R. Savitha, Dr.R.Vijayabhasker