A SOLUTION FOR EFFICIENT LOW POWER DESIGN

Abstract

In this paper, we propose a level-converting retention flip-flop (RFF) for ZigBee systems-on-chips

(SoCs). The proposed RFF allows the voltage regulator that generates the core supply voltage (VDD,core) to be

turned off in the standby mode, and it thus reduces the standby power of the ZigBee SoCs. The logic states are

retained in a slave latch composed of thick-oxide transistors using an I/O supply voltage (VDD,IO)that is always

turned on. Level-up conversion from VDD,core to VDD,IO is achieved by an embedded nMOS pass-transistor

level-conversion scheme that uses a low-only signal-transmitting technique. By embedding a retention latch and

level-up converter into the data-to-output path of the proposed RFF, the RF Fresolves the problems of the static

RAM-based RFF, such as largedc current and low readability caused by threshold drop. The proposed RFF does not

also require additional control signals for power mode transitioning.

Author

KANNAN.M