AN EFFICIENT PROTECTION FOR FPGA IP CORE USING PHYSICAL UNCLONABLE FUNCTION

Abstract

In VLSI circuit design, one of the very important aspects is to deal with proliferation of ICs for
their security. This project proposes an efficient protection for FPGA IP core using PUF. The main objective
of this project is to protect the FPGA from the cloning, copying and other side channel attacks. PUF is used
for low cost authentication and the security key generation.This optimization technique thus has reduced
delay, power and area. The ring oscillator is used in this system for stabilizing the PUF. RO-PUF can
support a high number of challenge/response pairs without impacting excessively the area of the PUF. ROPUF uses SRAM which is significant improvement to this project. The software used in this project is
Xilinix which enables the developer to synthesize their designs. Xilinix productivity advantage helps
efficiently migrate the FPGA designs to hardware platform. The modified FSM only introduces 1.089ns gate
delay and 0.034% power overhead on average for ten FSM designs.

Author

T.Ragavi, Dr.R.Vijayabhasker