DESIGN OF CONVENTIONAL 8 TAP FIR FILTER AND ANALYSIS OF ASYNCHRONOUS PARALLEL SELF - TIMED ADDER

Abstract

In VLSI circuit design, reduction of power dissipation, area and delay is the major goal,
regardless of its realization techniques, results in energy dissipation due to the information loss. The
objective of the project is to design of PASTA (Asynchronous Parallel Self-Timed Adder). It is regular and
uses Half-Adders (HAs) along with multiplexers requiring minimal interconnections. This PASTA design is
used for designing FIR filter. The design having the high speedup circuitry for addition. The coding for FIR
filter is developed and done by using conventional method. It contains 8 TAP design so that addition process
can be much effective. The power distribution and gate count can be optimized. The output waveform for the
8 Tap FIR filter is simulated. Simulations have been performed using an XILINX 14.1 version that verifies
the practicality and superiority of the proposed approach over existing adders. The on chip power
consumption of 8TAP filter is achieved as 0.034w.

Author

G.Valli, Dr.R.Vijayabhasker