LOW COMPLEXITY ASYNCHRONOUS DOMINO LOGIC PIPELINE DESIGN BASED ON HYBRID DATA PATH

Abstract

The VLSI systems become more and more complex, because of the physical design issues. The
Asynchronous design is considered as a promising solution for dealing with this issues that relate to the
global clock. The main objective of the project is to design low complexity, high-throughput and ultralowpower asynchronous domino logic pipeline design using Efficient Charge Recovery Logic (ECRL). ECRL
implement the logic function of the stage instead of Synchronizing Logic Gate (SLG) gates. In the
asynchronous circuit, ECRL gates acquire power and become active only when performing useful
computations, and idle ECRL gates are not powered and thus have negligible leakage power dissipation. The
tanner software is used to draw the semantic diagram of 8 × 8 array style multiplier to evaluating the
efficient pipeline method. The overall power consumption were reduced, it save 25% to 30% power in both
worst case delay and best case delay.

Author

N.Priya, Dr.R.Vijayabhasker