SIGNAL INTEGRATING AND TANDBY POWER REDUCTION BY CMOS RFF
Abstract
In this paper, we propose a level-converting reten- tion flip-flop (RFF) for ZigBee systems-onchips (SoCs). The proposed RFF allows the voltage regulator that generates the core supply voltage
(VDD,core) to be turned off in the standby mode, and it thus reduces the standby power of the ZigBee
SoCs. The logic states are retained in a slave latch composed
of thick-oxide transistors using an I/O supply voltage (VDD,IO) that is always turned on. Level-up
conversion from VDD,core to VDD,IO is achieved by an embedded nMOS pass-transistor levelconversion scheme that uses a low-only signal-transmitting technique. By embedding a retention latch and
level-up converter into the data-to-output path of the proposed RFF, the RFF resolves the problems of
the static RAM-based RFF, such as large dc current and low readability caused by threshold drop. The
proposed RFF does not also require additional control signals for power mode transitioning. Using 0.13-µm
process technology, we implemented an RFF with VDD,core and VDD,IO of 1.2 and 2.5 V, respectively. The
maximum operating frequency is 300 MHz. The active energy of the RFF is 191.70 fJ, and its standby
power is 350.25 pW.
Author
Anandhi.T,Kumar.S
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