DESIGN AND IMPLEMENTATION OF MULTIPLIER USING DUAL VALUE LOGIC

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DESIGN AND IMPLEMENTATION OF MULTIPLIER USING DUAL VALUE LOGIC

Abstract

A general method of synthesis and simulation of Different pass transistor Network topologies are analysed. In digital signal processing application, multiplier is one of the critical parts. The recent advancements in CMOS technology indicate a strong need for high speed, high density, low power, low cost multiplier design for ubiquitous use in majority of leading-edge commercial applications. This paper proposed the comparison of an 8- bit multiplier design such as CMOS full adder, Double pass transistor (DPL) and Dual Value Logic (DVL). The investigation is carried out with simulation runs on HSPICE environment using 90 nm process technologies at 25 °C.

Author

S. Vignesh Dr. R. Vijayabhasker

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International Journal of Advanced
Science and Engineering Research

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