DESIGN OF LOW POWER CMOS COMPARATOR FOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER

Why publish with

ijaser

IJASER publishes high-quality, original research papers, brief reports, and critical reviews in all theoretical, technological, and interdisciplinary studies that make up the fields of advanced science and engineering and its applications.

DESIGN OF LOW POWER CMOS COMPARATOR FOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER

Abstract

Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) circuits are extensively used today because of the need to translate analog signal to digital signal and vice versa. A comparator plays a basic role in most electronic applications. A CMOS comparator using dynamic latch, suitable for high-speed Analog-to-Digital Converter (ADC) with high speed and low power dissipation is presented. The design is intended to be implemented in Sigma-delta ADC. The design has been carried out in Tanner EDA tools, the schematic simulation is done using Schematic Editor (S-Edit) and layout simulation of the design is verified using Layout Editor (L-Edit) using 90nm CMOS technology. Simulation results are done with supply voltages of 1.6V and 2.0V respectively. It is found that the power is least dissipated in 1.6V which is 0.7899 mW, but it has the longest propagation delay of 0.715 ns. In contrast, the 2.0V supply produced 1.471 mW and a shorter delay of 0.550 ns.

Author

RAM NARAYANAN JAYAKUMAR VIJAYARAGAVAN VIVEK NAPOLEAN

Download

International Journal of Advanced
Science and Engineering Research

For Queries/Clarification

Why publish with

Author's Desk

Downloads