LOW POWER MULTI-BIT FLIP-FLOPS DESIGN FOR VLSI CIRCUITS
Abstract
Power has become a burning issue in modern VLSI design. In modern integrated circuits, the power consumed by clocking gradually takes a dominant part. In proposed method, by using Multi bit flip- flop method we can reduce its power consumption by replacing some flip-flops with fewer registers. However, this procedure may affect the performance of the original circuit. Hence, the flip-flop replacement without timing and placement capacity constraints violation becomes a quite complex problem. To deal with the difficulty efficiently, we have proposed several techniques. First, we perform a co-ordinate transformation to identify those flip flops that can be merged and their legal regions. Besides, we show how to build a combination table to enumerate possible combinations of flip-flops provided by a library. Finally, we use a hierarchical way to merge flip-flops. Besides power reduction, the objective of minimizing the total wire length is also considered. The Main objective is to achieve the Clock Power Reduction by using Multi bit flip flop method and Minimizing the total Wirelength.
Author
K. MALATHI
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