AREA EFFICIENT HIGH SPEED TRANSPOSE FORM FIR FILTER ARCHITECTURE FOR FIXED AND RECONFIGURABLE APPLICATIONS

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AREA EFFICIENT HIGH SPEED TRANSPOSE FORM FIR FILTER ARCHITECTURE FOR FIXED AND RECONFIGURABLE APPLICATIONS

Abstract

The main objective of the work is to design transpose form Finite Impulse Response (FIR) filters. Which are pipelined and always support Multiple Constant Multiplications (MCM) technique that results in saving of computation. Transpose form of filter configuration does not directly support the block processing method. Transpose form of block FIR filter is depends on the multiplier based architecture for reconfigurable applications. Block-processing method is used to support highthroughput hardware structures. The MCM architecture is also presented for the block implementation of fixed FIR filters. The MCM method is used to reduce the total number of additions required for the realization of multiplications using common sub expression sharing. Sub expression sharing means a given input is multiplied with a set of constants. The MCM method is more effective, when a common operand is multiplied with multiple number of constants. The proposed structure involves 11% less ADP and 10% less EPS than that of the existing direct-form block FIR structure. The result of the reconfigurable and fixed FIR filter architecture is simulated and verified using ModelSim 6.5b and Xilinx 8.1i ISE softwares.

Author

Aishwarya.J , Vijayabhasker.R

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International Journal of Advanced
Science and Engineering Research

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