In many DSP applications, the design of Multiply and accumulate (MAC) unit defines the efficiency of the overall system. Similarly Multiple Constant Multiplication (MCM) is the multiplication operation between the particular input variable and the variable coefficients constants, which is used in FIR filters. This MCM is performed by using constant multiplier, which is implemented using some prior algorithms. Variable-bit BCSE algorithms is the one which belongs to BCSE algorithm. In this method parallel prefix computation logic is used for the addition process in Vertical-Horizontal Binary Common Sub-expression Elimination (VHBCSE) based constant multiplier design. In this paper ripple carry adder (RCA) is replaced by the parallel prefix adders (PPA) like a Brent Kung adder (BKA) and Ling adder in the PPG and control addition layer. The VHDL language is used to design the constant multiplier, using ripple carry adder, Brent Kung adder and Ling adder. Thus the comparison between this different design in terms of performance parameters like power, delay and area is achieved by the FPGA implementation using Xilinx ISE 9.2i synthesis tool.