In this paper we suggest hybrid full adder circuits using new XNOR, XOR gates. Compared to existing circuits, these circuits are designed to be of high speed and less power consumption. This is possible because of the low capacitance of the output. Each of the Full Adder circuits proposed has its own advantages of size, power consumption and driving ability. In Tanner tool simulations are performed in 65-nm technology. From the results, it is found that the circuits proposed are better than the existing ones. The performance of proposed full adder circuits is also analyzed by varying the voltage of supply and the load of output.