Viterbi decoders are widely used in digital communication which dissipates huge quantity of power. High speed and low power of system can be achieved by applying asynchronous technique to the digital system. In this work we have designed VD with 4-state, 1/2-code rate synchronous and asynchronous Viterbi decoder. Dynamic power can be lower by reducing switching activity and this is occurring due to designing VD from Hybrid Register Exchange Method. Soft decision decoding technique is being used since it can correct more number of errors than hard decision. Results shows that the implemented design using GALS gives 13.04% reduction in dynamic power consumption compared with its synchronous counterpart with improvement in maximum frequency. ACS as follows. 1) By predefining the bus of distances in BMU 2) By recursive implementation Add-Compare-Select (ACS) of PMU. i.e. Area optimized BMU and PMU (ACS) units are implemented using VLSI front end and back end design tools. While implementing it is also verified that the decoder is error resistant. It is also observed that backend switch level design implementation is more area and power efficient than the front-end RTL design.