The newly proposed posit number system is more precise and can provide a broader dynamic range than the conventional IEEE754-2008 floating-point numbers. It is non-uniform data representation makes it suitable in deep learning applications. Posit adder and posit multiplier have been well developed recently in the collected works. The proposed generator can generate VHDL code of posit MAC unit for any given total bit width and exponent bit width. In this paper, we propose the architecture of a 16 - bit modified posit multiplier and adder, which results in less power consumption. In the posit multiplier, our work relates to the mantissa multiplier. The mantissa multiplier is designed for maximum possible bit-width, where the entire multiplier is divided into smaller ones. Only the required smaller adders and multipliers are used during the run time. So reduce the area, power and timing overhead. The Modelsim 10.5, Xilinx ISE 9.2i software tools are used in simulation and synthesis process.